1. Field of the Invention
This invention relates generally to the structure and fabrication process of semiconductor power transistors. More particularly, this invention relates to a novel and improved polysilicon-oxide layer structure in the termination area of a power to eliminate defects in the oxide layer whereby the reliability difficulties and product yield problems caused by oxide layer defects may be resolved.
2. Description of the Prior Art
Device performance and production yield in manufacturing the power MOSFET devices are adversely affected by the inherent vulnerable spots typically occurred near the bottom edges of a thick oxide layer where the thick oxide layer disposed immediately adjacent to a thinner gate oxide. The inherent vulnerability at these thick-thin oxide layer intersection points is caused by a stress induced from thermal expansion differences during the temperature cycles occurred in manufacturing the MOSFET device. Subsequently, small cracks or layer peeling-off at these vulnerable spots are subject to further damages when exposed to etchants in patterning the gates. Furthermore, processing residual are likely to be trapped in the cracks or holes formed in the vulnerable spots thus contaminating the MOSFET device and causes a performance degradation.
Referring to FIG. 1A for a typical cross sectional view of a power MOSFET device. This conventional N-channel MOSFET device 10 is supported on a n.sup.+ substrate 15 with a n.sup.- doped epitaxial drain region 20 formed thereon. A plurality of p-body regions 25 and n.sup.+ source regions 30 are formed on top of the drain region 20 as shown. The MOSFET device 10 is divided into an active area 40 which includes a core cell area 42 and a gate contact area 44. The MOSFET device 10 further includes a field oxide area 50. A plurality of cells which include the p-body 25, the source regions 30, and a polysilicon gate 35 are formed in the core cell area 42 padded by a thin oxide layer 36. As shown in FIG. 1, the source electrode (S) 60 is formed in the core cell area 42 and the gate runner (G) 76 and the gate contacts 70 are formed in the gate contact areas 44 in the active area 40 near the field oxide areas 50. The field plate (FP) 80 and the equal ring (EQR) 90 are formed in the filed oxide area 50 where the field oxide layer 52 is not removed in the manufacturing process. FIG. 1B is an exploded cross sectional view of the portion near the thick oxide layer 52 in the termination area 50. Particularly, there are inherent weak points 99 around the intersection between the thick oxide layer 52 and the gate oxide layer 36. Due to the structure damage, a drain to source leakage current occurs as that shown in FIG. 1C. Fig. Due to this structural damage, an undesirable leakage current, i.e., I.sub.DS, as that shown FIG. 1C, is experienced before a P-N junction avalanche breakdown occurs.
There are several reasons that damages are likely to occur near the weak points 99 where the thick oxide layer 52 joins the thinner gate oxide layer 36. An etch step is first applied for patterning the thick oxide layer i.e., the initial oxide layer 52 to remove the initial oxide layer 52 from the active area. Then a thinner gate oxide layer 36 is formed. The gate oxide layer 36 and initial oxide layer 52 have different thermal expansion coefficients because of the differences in thickness. Inherent vulnerable spots 99 are formed near the areas where the initial oxide layer 52 joins the thinner oxide layer. As the MOSFET transistor is subject to up-and-down temperature cycles, a stress is experienced in these vulnerable spots due to differences in thermal expansions in these thermal cycles. Micro-cracks or surface damages are likely to occur in these areas. After the formation of the thin gate oxide, polysilicon gates may be patterned by dry etch. Further damages to the edge surface near the bottom of the thick oxide layer may be induced when exposure to plasma etchants. The damaged surface with cracks and holes may then become traps for different kinds of processing residuals. The damaged areas thus become depository sites for contaminants. For those reasons, poor layer integrity of the thick oxide layer 52 has often occurred and the deposited contaminants also cause an undesirable drain to source leakage current.
Conventional manufacture method does not provide a layer structural feature or method to overcome this difficulty. Typical layer structure near a terminal area is shown in FIG. 2 as that disclosed in U.S. Pat. No. 4,593,302 by Lidow et al. entitled "Process for Manufacture of High Power MOSFET with Lateral Distributed High Carrier Density Beneath the Gate Oxide" (issued on Jun. 3, 1986). FIG. 2 shows that a thick oxide layer 131 with a polysilicon layer 132b formed thereon near a termination area. The same difficulties as described above would also occur for the same reasons near the bottom portions of the thick oxide layer 131 in this patented layer structure by Lidow et al. Weak points susceptible to layer surface damages due to stress caused by different thermal expansions between thick and thin oxide layers and exposure to plasma etchant for gate formation are existing difficulties not properly addressed by those of ordinary skill in the art of power MOSFET device manufacture.
Therefore, a need still exists in the art of power device fabrication, particularly for semiconductor power device design and fabrication, to provide an improved gate structure and fabrication process that would resolve these difficulties.